1. Field of the Invention
The present invention relates to a mounting technology of a semiconductor device.
2. Description of the Related Art
Various types of information equipment such as large-scale computers, personal computers, and mobile devices are becoming increasingly sophisticated and downsized year by year. Semiconductor devices mounted on such equipment are therefore required to have as many elements, interconnects, and terminals as possible within a limited size range. There is however a problem that when interconnects are made smaller, a distance between them inside a semiconductor device decreases, leading to an increase in an electrostatic capacitance between adjacent interconnects. A technology using a material having a low electric permissivity as an insulating material disposed between interconnects is developed in order to overcome this problem.
As a technology of closely contacting and connecting a terminal of a semiconductor element with a substrate on which the semiconductor element is to be mounted, there are developed a connection structure using a solder ball which structure is disclosed in “Japan Electronics and Information Technology Industries Association, Japan Jisso Technology Roadmap 2007”, a connection structure using protrusions disposed on the surface of a semiconductor element to connect the protrusions with the substrate, and a connection structure using a solder ball having a core inside thereof which structure is disclosed in Japanese Patent Laid-Open No. 103156/1999.
The reliability of connections in products having semiconductor mounted thereon is governed by numerous factors such as connection structure, shape or size of each member, materials composing each member, and the like. As a technology of balancing these many factors including them, there is developed Taguchi's method which is disclosed in “Takayoshi Kashiwamura, et al., Optimization of nonlinear problem in Taguchi's method, published by Asakura Publishing Co., Ltd.”. In this method, experiments are made on conditions determined using an orthogonal array, whereby effects of each factor can be assessed efficiently without carrying out many experiments. When respective effects of many factors are independent each other, assessment can be made with high accuracy. A large interaction between these factors, on the other hand, leads to low accuracy.
Accordingly, when respective factors are balanced by using this method, it is effective to clarify the mechanism of a phenomenon to be assessed in advance and extract factors which are independent each other (or factors or ranges regarded to be independent from each other). Even if the method is applied to a phenomenon having an unknown mechanism, it is difficult to balance these factors.
Porous materials have been developed as a material having a low electric permittivity and used for insulating materials between interconnects of a semiconductor element. In general, these porous materials have a high porosity in order to attain a sufficient low electric permittivity so that their material strength is low. Insulating materials are placed as a thin insulating layer over the surface of a semiconductor element. They have, inside thereof, an interconnect structure such as multilayer interconnect and interconnects are positioned at a distance as minute as from several μm to several tens nm. Further, the insulating layers have, over the surface thereof, connection terminals such as a metal land to a substrate, each made of copper or aluminum etc.
Silicon, that is, a material of the semiconductor element, has a linear coefficient of expansion of about 3 ppm/K, while copper and aluminum have linear coefficients of expansion of about 17 ppm/K and about 23 ppm/K, respectively. When the temperature near the insulating layer changes due to the behavior of semiconductor or change in the environmental temperature, a stress attributable to a difference in thermal deformation between silicon and the land occurs in the insulating layer. When this stress increases and exceeds the strength of the insulating material, cracks appear in the insulating layer and cause short-circuit or disconnection. Therefore, it becomes a major object to reduce a stress which will occur in the insulating layer and prevent the breakage of the insulating layer, thereby securing the reliability of a semiconductor device.